1. Field of the Invention
The present invention relates generally to a method for manufacturing semiconductor memory devices, and more particularly to a method for manufacturing a capacitor of a highly integrated semiconductor memory device having increased cell capacitance provided by grains formed within polycrystalline silicon layers.
2. Description of the Prior Art
In case of DRAMs, increased cell capacitance improves the R/W capability and decreases the soft error rate in a memory cell, so it plays an important role in the improvement of a cell's memory characteristics. Due to increased packing density in memory cells, unit cell area has decreased per chip, which in turn reduces the area available for the cell capacitor. Therefore, the increase of capacitance per unit area together with increased packing density are necessary in tandem.
In recent years, many research reports have been issued concerning increased cell capacitance, most of them related to the structure of the cell capacitor's storage electrode. They include: the fin-structure electrode of Fujitsu Co., the BOX structure and SSC (Spread-Stacked Cell) structure electrodes of Toshiba Co., and the cylindrical structure electrode of Mitsubishi Co. However, attempts to increase cell capacitance by improving the structure of the storage electrode, have met with problems such as limitation of minimum feature size and a high error rate involved in complex manufacturing processes. It is accordingly doubtful whether an improved structure of a storage electrode is practical. Yet, in order to overcome the aforesaid problems, the need for a new manufacturing method for a cell capacitor increases further.
A method for increasing cell capacitance has been proposed which utilizes the physical properties of the material forming the storage electrode independently of the structural improvement of the storage electrode. An example was presented in the 1990 IEEE entitled "A capacitor-over-bit line (COB) cell with a hemispherical-grain storage node for 64 Mb DRAMs" by NEC Co. of Japan.
FIG. 1 is a layout used for manufacturing the COB cell structure described in the above paper. The layout is not the main object of the present invention, but it will be described for its useful effect in manufacturing the device of the present invention.
The region designated by a laterally extending single-dotted line is a mask pattern P1 for forming an active region. The regions defined by solid lines are symmetrically arranged around a longitudinal center and represent a mask pattern P2 for forming gate electrodes. The regions designated by long-dashed lines in the shape of two arms of a vane balancing around the longitudinal center are a mask pattern P3 for forming local interconnects by which a source region is connected to a storage electrode. The region defined by a laterally extending double-dotted line which has a contact mark therein, represents a mask pattern P4 for forming a bit line. The regions designated by short-dashed lines surrounding oblique-lined areas are a mask pattern P5 for forming the storage electrode.
The COB (Capacitor-Over-Bit line) cell is one where a cell capacitor is formed over a bit line, and the process for COB manufacturing is as follows. After the bit line is formed to be connected to a drain region of a transistor, the bit line is electrically insulated by coating an insulating material on the whole surface of a substrate. Then, the insulating material is partially removed, thereby exposing the region electrically connected to the source region of a transistor. In doing so, a storage electrode is formed on the insulating material, and is connected to the source region of the transistor through the partially exposed portion of the insulating material. This is suitable for 64 Mbit and 256 Mbit DRAM cells, and was introduced for preventing bit line contact failures.
FIG. 2A to FIG. 2D are cross sectional views illustrating a conventional method for manufacturing a capacitor of a highly integrated semiconductor memory device.
The polycrystalline silicon with hemispherical-grains described in the above-mentioned paper (hereafter, referred to as HSG polycrystalline silicon) is formed by means of physical phenomena especially occurring while amorphous silicon is in a transitional state to polycrystalline silicon. When amorphous silicon is deposited on a semiconductor substrate and then annealed, the amorphous silicon forms minute hemispherical-grains, under specified conditions: 550.degree. C. at 1.0 torr. Then, the surface of the amorphous silicon upon an intermediate state becomes uneven polycrystalline silicon which increases the surface area to two or three times that of the smooth surface thereof.
FIG. 2A shows an insulating layer 22 (strictly speaking, two or three stacked insulating layers) formed over the whole surface of the semiconductor substrate 10, on which both a local interconnect 20 in contact with the source region of a transistor and a bit line in contact with the drain region, have been formed. Thereafter, a contact hole 9 is formed by anisotropic etching in order to expose a portion of the local interconnect. Then, the contact hole is completely filled with a first polycrystalline silicon which is formed to a predetermined thickness on the insulating layer. Finally, an etching process is performed, using the mask pattern P5, whereby a core storage electrode 30 is formed per each cell unit.
FIG. 2B shows an HSG polycrystalline silicon layer 32 formed over the whole surface of the substrate 10 on which the core storage electrode 30 has been formed. This is formed by an ordinary method, e.g., LPCVD (Low-Pressure Chemical Vapor Deposition) under specified conditions of temperature and pressure, i.e., at 550.degree. C. and 1.0 torr, respectively. Because of the small hemispherical grains, the effective area of the HSG polycrystalline silicon layer is increased to roughly twice that of conventional polycrystalline silicon layers without the HSG. Here, since the HSG is about 80nm in diameter, the HSG polycrystalline silicon layer should be at least 80nm thick and should be narrower than half of a core storage electrode spacing.
FIG. 2C shows the HSG polycrystalline silicon layer 32 etched back by an RIE (Reactive Ion Etching) method, using HBr gas without any etching masks, and this is carried out until portions of the insulating layer 22 between each core storage electrode 30 are exposed to divide the storage electrode into cell units. Also during this step, the HSG polycrystalline silicon coated on the upper surface of the core storage electrode is completely removed and the surface is left uneven, but on the surface of the core storage electrode only. The HSG polycrystalline silicon 32a remaining on the side surfaces of the core storage electrode is somewhat smoothed. The storage electrode is formed by the core storage electrode having the uneven upper surface and the HSG polycrystalline silicon layer 32a remaining on the side surfaces of the core storage electrode after the etching process.
After a dielectric film 34 is formed (see FIG. 2D) on the whole surface of the storage electrode, a plate electrode 36 is formed by coating a second polycrystalline silicon on the whole surface of the structure obtained by the above, whereby the cell capacitor is completed.
In the above-described method for manufacturing a capacitor of a memory cell, the physical properties of the material forming the storage electrode are used, independently of the structural improvement of the storage electrode, to extend the effective area of the cell capacitor. Therefore, the above scheme is advantageous because cell capacitor formation is simplified and free from limitations of minimum feature size. However, required processing conditions, necessary for successful product formation such as the specific temperature and pressure, demand that a margin of error during processing be overly narrow. Moreover, an increase of effective capacitance per unit area is limited to approximately two times that of previous methods.